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CD4527BMS
December 1992
CMOS BCD Rate Multiplier
Description
CD4527BMS is a low power 4-bit digital rate multiplier that provides an output pulse rate which is the clock input pulse rate multiplied by 1/10 times the BCD input. For example, when the BCD input is 8, there will be 8 output pulses for every 10 input pulses. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversion, and frequency division. For fractional multipliers with more than one digit, CD4527BMS devices may be cascaded in two different modes: the Add mode and the Multiply mode (see Figures 9 and 11). In the Add mode,
Output Rate = (Clock Rate) [0.1BCD1 + 0.01BCD2 + 0.001BCD3 + . . .]
Features
* High Voltage Type (20V Rating) * Cascadable in Multiples of 4-Bits * Set to "9" Input and "9" Detect Output * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Standardized Symmetrical Output Characteristics * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
In the Multiply mode, the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second one,
e.g. 9 10 x 4 10 = 36 100 or 36 output
Applications
* Numerical Control * Instrumentation * Digital Filtering * Frequency Synthesis
pulses for every 100 clock input pulses. The CD4527BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W
Pinout
CD4527BMS TOP VIEW
Functional Diagram
BCD RATE SELECT INPUTS "9" OUT C D 1 2 3 16 VDD 15 B 14 A 13 CLEAR 12 CASCADE 11 INHIBIT IN (CARRY) 10 STROBE 9 CLOCK 1 7 INHIBIT (CARRY) OUT ABCD 14 15 2 3 9 10 STROBE 12 CASCADE
CLOCK INHIBIT 11 (CARRY) IN SET TO 4 NINE CLEAR 13
SET TO "9" 4 OUT OUT INHIBIT OUT (CARRY) VSS 5 6 7 8
/10
COUNTER
RATE SELECT LOGIC
6 5
OUT OUT RATE OUTPUTS
"9" OUT
VSS = 8 VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3343
7-1216
Specifications CD4527BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
VOH > VOL < VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1217
Specifications CD4527BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN 1.2 .89 MAX 300 405 760 1026 180 243 200 270 UNITS ns ns ns ns ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock to Output Propagation Delay Clear to Output Propagation Delay Cascade to Output Transition Time
SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TTHL TTLH FCL
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
Maximum Clock Input Frequency NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V MIN MAX 5 150 10 300 10 600 50 UNITS A A A A A A mV
7-1218
Specifications CD4527BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage High Propagation Delay Clock to Output Propagation Delay Clear to Output Propagation Delay Cascade to Output Propagation Delay Clock to Out SYMBOL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL TPLH CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Propagation Delay Clock to INHIBIT Out TPHL VDD = 5V VDD = 10V VDD = 15V Propagation Delay Clock to INHIBIT Out TPLH VDD = 5V VDD = 10V VDD = 15V Propagation Delay INHIBIT IN to INHIBIT Out Propagation Delay Clock to "9" or "15" Out TPHL TPLH VDD = 5V VDD = 10V VDD = 15V TPHL TPLH VDD = 5V VDD = 10V VDD = 15V Propagation Delay Set to Out TPHL TPLH VDD = 5V VDD = 10V VDD = 15V Transition Time TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Inhibit Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Maximum Clock Rise and Fall Time TRCL TFCL VDD = 5V VDD = 10V VDD = 15V NOTES 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 TEMPERATURE +25oC, +125oC, -55oC +25oC +25oC +25oC +25 C +25oC +25oC +25 C +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o o o
MIN +7 2.5 3.5 -
MAX 150 120 350 260 90 70 220 110 90 640 290 200 500 200 150 260 120 90 600 250 180 660 300 220 100 80 100 40 20 240 130 110 330 170 100 15 15 15
UNITS V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns s s s
Maximum Clock Input Frequency Minimum Data Setup Time - Inhibit
7-1219
Specifications CD4527BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clear Removal Time SYMBOL TREM CONDITIONS VDD = 5V VDD = 10V VDD = 15V Minimum Set Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Set or Clear Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25 C +25oC
o o
MIN -
MAX 60 40 30 150 80 50 160 90 60 7.5
UNITS ns ns ns ns ns ns ns ns ns pF
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
7-1220
Specifications CD4527BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 1, 5-7 1, 5-7 1, 5-7 GROUND 2-4, 8-15 8 2, 4, 8, 10, 12-15 8 VDD 16 2-4, 9-16 3, 16 2-4, 9-16 1, 5-7 9 11 9V -0.5V 50kHz 25kHz
7-1221
CD4527BMS Logic Diagram
14* A 15* B 2* C 3* D 11* INHIBIT IN
VDD VSS = 8 VDD = 16
VSS
*
ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK
T C A R
Q Q STROBE CASCADE 10 12 R1 OUT 6
*
*
R2 9* CLOCK T C B R Q Q
OUT 5 R3 T C S C R Q Q R4
4* SET TO "9" T C S D R Q Q
"9" 1 INHIBIT OUT 7
13* CLEAR
FIGURE 1.
7-1222
CD4527BMS
TRUTH TABLE INPUTS NUMBER OF PULSES OR INPUT LOGIC LEVEL (0 = Low; 1 = High; X = Don't Care) D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X 1 0 X C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X X X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X CLK 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 INH IN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 STR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 CAS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CLR * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 SET * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OUTPUTS NUMBER OF PULSES OR OUTPUT LOGIC LEVEL (L = Low; H = High) OUT L 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 ** L H 10 L L OUT H 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 ** H *** 10 H H INH OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L "9" OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ** 1 1 L L H
* Clear and Set Inputs should not be high at the same time; device draws increased quiescent current when in this non-valid state. ** Depends on internal state of counter. *** Output same as the first 16 lines of this truth table (depending on values of A, B, C, D).
Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
7-1223
CD4527BMS Typical Performance Characteristics
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0
(Continued)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0
0 -5 -10 -15
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
105 8 POWER DISSIPATION PER (PD) (W)
6 4 2
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V
200
AMBIENT TEMPERATURE (TA) = +25oC
104 8
6 4 2
10V 10V 5V
150 SUPPLY VOLTAGE (VDD) = 15V 10V 100
103 8
6 4 2
5V 50
10
2
8 6 4 2
CL = 50pF CL = 15pF
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
10 1 10 102 103 INPUT FREQUENCY (fIN) (kHz) 104
0
20
40 60 80 LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK OR STROBE TO OUT)
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
7-1224
CD4527BMS Applications
MOST SIGNIFICANT DIGIT DRM 1 0 0 1 A B C D CLOCK CASC. INH. IN ST CLEAR "9" S INH. OUT OUT OUT 1 0 0 1 0 A B C D CLOCK CASC. INH. IN ST CLEAR "9" S TIMING DIAGRAM SHOWING ONE OF FOUR OUTPUT PULSES CONTRIBUTED BY DRM 2 TO OUTPUT FOR EVERY 100 CLOCK PULSES IN FOR PRESET NO. 94 INH. OUT OUT OUT 012345678901234567890 CLOCK OUT DRM 2 LEAST SIGNIFICANT DIGIT DRM 2
CLOCK
FIGURE 9. TWO CD4527BMS's CASCADED IN THE "ADD" MODE WITH A PRESET NUMBER OF 94
(
9 10
+
4 100
=
94 100
)
DRM 1 0 0 1 A B C D CLOCK CASC. INH. IN ST CLEAR
1 0 OUT OUT INH. OUT 0 1 0 A B C D
DRM 2 OUT OUT INH. OUT
CLOCK CASC. INH. IN
"9" S
ST CLEAR
"9" S
CLOCK
FIGURE 10. TWO CD4527BMS's CASCADED IN THE "MULTIPLY" MODE WITH A PRESET NUMBER OF 36
(
9 10
x
4 100
=
36 100
)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1225
CD4527BMS Timing Diagram
012345678901234 CLOCK Qa Qb Qc Qd R1 R2 R3 R4 OUTPUT (PIN 6) A ENABLED B ENABLED C ENABLED D ENABLED INH. OUT OUTPUT (PIN 6) PRESET NO. OF 1 PRESET NO. OF 2 PRESET NO. OF 3 PRESET NO. OF 4 PRESET NO. OF 5 PRESET NO. OF 6 PRESET NO. OF 7 PRESET NO. OF 8 PRESET NO. OF 9
FIGURE 11. (SEE LOGIC DIAGRAM)
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION: BOND PADS:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1226

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